1. Field of the Invention
The present invention relates to the formation of multilevel interconnect structures of the type that are found in high density integrated circuit deices.
2. Description of the Related Art
High density integrated circuits are made up of devices, such as field effect transistors (FETs) and bipolar devices formed in and on a semiconductor substrate, and the multilevel interconnect structures that are used to form connections to and between the various devices in and on the semiconductor substrate. Many high density integrated circuits include closely spaced arrays of devices that are accessed by and connected to one or more arrays of parallel wiring lines formed above the substrate and the devices. Arrays of closely spaced wiring lines are familiar features of integrated circuit memories such as nonvolatile memories like ROM, EEPROM and flash EEPROM, dynamic random access memories (DRAM) and static random access memories because of the regularity of these circuits. Because of the requirements of routing interconnects efficiently while using a few layers of interconnects as is possible, parallel arrays of wiring lines are also featured in digital signal processors, microprocessors and even more random sorts of logic circuits.
For all sorts of these various applications, how wide wiring lines are made and how closely the wiring lines can be spaced are significant considerations in determining the size and cost of the final integrated circuit. Simply put, reduced design rules tend to produce smaller and less expensive integrated circuits. Additionally, reduced design rules affect how connections are made to wiring lines and how different levels of wiring lines can be interconnected. For example, in many multilevel interconnect designs, it is conventional to provide a wider portion of a wiring line in those regions where a vertically extending interconnect is to be formed. Thus, if a vertical interconnect is to be formed between the end of a first level wiring line and a second level wiring line separated by an intermetal dielectric layer, a square or circular pad might be provided at the end of the first level wiring line that is wider than the rest of the first level wiring line. After the first level wiring line is formed, the intermetal dielectric layer is provided and then a via is formed through the intermetal dielectric layer to expose within the via a portion of the pad on the end of the first level wiring line. Metal is provided to fill the via and then a wiring line is formed over the metal plug within the via to complete the connection. Providing such a "dog bone" shaped structure for the first level wiring line increases the alignment and lithography process margins for the processes used in forming the interconnect structure. The cost of providing such a "dog bone" shaped structure is that the wiring lines cannot be spaced as closely together due to the increased width of the wiring line associated with the pad. For aggressive device designs, it is undesirable to provide an oversized portion of a wiring line to facilitate the easier formation of vertically extending metal interconnects.
On the other hand, when wiring lines are made to have a width near or at the resolution limit of the particular lithography process being used in forming the device, it is likely inevitable that unlanded vias will be formed when the vias are formed without an enlarged contact pad. Unlanded vias are ones that extend over the edge of a metal wiring line or other conductor to which the desired connection is to be made. Such unlanded vias are in many ways inevitable because the vias are formed having a width that is approximately the same as the wiring lines that are being contacted so that essentially perfect alignment is necessary to align the via to the wiring line if an unlanded via is to be avoided. Any misalignment of the via results in a portion of the via being positioned over the edge of the wiring line and, hence, unlanded. Aspects of conventional via formation problems are illustrated in FIGS. 1-3. FIG. 1 illustrates one extreme of the unlanded via problem. An interlayer dielectric 20 covers a substrate 10 and has a first level wiring line 22 on its surface, with both the first level wiring line 22 and the interlayer dielectric 20 covered by a layer of an intermetal dielectric 24. Typically, the intermetal dielectric layer 24 is an oxide of silicon. The FIG. 1 structure is formed by depositing a layer of interlayer dielectric 20 over the semiconductor substrate 10 in which devices (not shown) including, for example, field effect transistors are provided. Metal or other wiring lines 22 are formed on the surface of the interlayer dielectric 20 by blanket depositing a layer of metal and patterning the metal into wiring lines using conventional photolithography. The intermetal dielectric layer 24 is then deposited, for example using chemical vapor deposition from a TEOS source gas, and vias 26 are formed through the intermetal dielectric 24 where interconnects are to be formed between the first level wiring line 22 and the wiring lines 28 or other conductors formed on the surface of the intermetal dielectric 24.
Vias for the vertical interconnect structure are typically formed through the intermetal dielectric layer 24 in a fixed time etching process, often using a fluorine based etchant which readily etches the oxide intermetal dielectric 24 and which does not etch metals. The via etch process typically is designed to include a sufficient level of overetch to ensure that the surface of the first level wiring line is cleared in the via etch process. It is generally impractical to rely on optical or other endpoint detection mechanisms for determining the endpoint of the via etch process because such endpoint detection processes are difficult. For example, if a fluorine based etchant is used to etch through an oxide to an underlying aluminum layer, the etch is unlikely to produce a good endpoint detection signature because of the very low volatility of aluminum fluorides, which are the expected endproduct of the via etching operation. In addition, the signal levels for typical optical endpoint detection system are low, since the endpoint detection signal must be sensed remotely from a chamber that includes a plasma source which acts as a bright, broadband light source. Consequently, it may be difficult to detect etching endpoints with satisfactory reliability. By necessity then, via etching is often a fixed time operation which incorporates a predefined level of overetching by design. Thus, for any misalignment in the via etching process, the unlanded portion 30 of the via will be etched alongside the wiring line 22 and possibly into the interlayer dielectric 20 on which the wiring line 22 is formed. While the deep unlanded portion 30 of the via 26 shown in FIG. 1 might arise through poor process design, it might occur simply from variations in the etching process, variations in the thickness of the wiring line 22 or the intermetal dielectric 24, or variations in the composition or density of the interlayer dielectric 20. Because it might cause a short of the wiring line 22 to a structure formed below the wiring line, the deep unlanded portion 30 of the via 26 is undesirable.
FIG. 2 illustrates a problem that represents a different extreme of the conventional via etch process. The structure of FIG. 2 and the method of making the FIG. 2 structure are largely the same as those illustrated in FIG. 1, except that the via etch process has stopped short of reaching the surface of the wiring line 22 so that a metal plug formed within the via 26 will not connect the first level wiring line 22 to the second level wiring line 28. As was the case with the FIG. 1 structure, it is possible that the FIG. 2 structure might arise from bad design, such as by not allowing a sufficient overetch margin for the via etch process. On the other hand, it is possible that such a failure could arise while operating within the tolerances of all of the processes involved in making the device of FIG. 2. In fact, it is conceivable that both the FIG. 1 and the FIG. 2 types of errors could arise on a single wafer. As a practical matter, failures like those illustrated in FIGS. 1 and 2 which arise when processes are completed within designed ranges are more detrimental to production efficiency and are less easily remedied than are failures which occur because of out of range process steps.
FIG. 3 shows another type of failure mechanism in a vertical interconnect structure that can arise even when all of the interconnect formation processing steps are performed within their optimal ranges. The FIG. 3 failure mechanism arises simply because the via is unlanded. As illustrated, a narrow unlanded portion or "notch" 32 of the via extends partially along the side of the wiring line 22 by an amount that may reflect the extent of overetch provided by design in the interconnect formation process. Thus, the notch 32 of the via will arise frequently in practical manufacturing processes operated in their designed manner. The notch 32 may trap impurities that cannot normally be cleaned by etching or solvent cleans. These impurities can exit the notch 32 during subsequent processing steps in a manner that can contaminate a subsequently deposited barrier layer and can make it difficult to fill the via with a metal plug. As such, the absence of an enlarged landing pad on the first level wiring line can lead to poor quality interconnect structures or otherwise reduce yields even when the process steps are performed with a high level of process control. It is thus desirable to develop a more reliable method for forming multilevel interconnect structures.